The High-Voltage Switch (HVS) process technology is designed to fabricate a high-voltage relay circuit, and a high-voltage switch circuit. Both of these types of circuits are used in telecom. (wired telephone) products/applications. One of the primary devices fabricated in the HVS technology is a NDMOS with a 400 V breakdown.
One of the features of the 400 V NDMOS is that it requires a p-type in the bottom of the lightly-doped p-type device islands in which it is formed. The p-type layer in the bottom of the p-type island is used to provide enough charge to fully deplete the drain extension layer. The use of a p-type bottom layer to control the depletion of a p-type island due to substrate bias is described by Beasom, U.S. Pat. Nos. 4,923,820 and 4,807,012. This also applies to the general case of depleting the drain extension, or junction termination extension (JTE) layer in a relatively thin, lightly doped island. FIG. 1a shows a conventional drain. FIG. 1b shows a drain with drain extensions. Note the differences in size and shape between the depletion zone of FIG. 1a and the depletion zone of FIG. 1b. The drain/junction-termination extension is used to improve (raise) the breakdown voltage of the device by de-focusing the field formed at the edge of the pn junction in the drain region.
Another purpose for the use of the backside highly-doped p-type layer in the HVS process technology, is to provide shielding at the bottom of the device island to protect the devices from swings in the potential of the handle wafer under the bond oxide (which can vary in sign, and may be in the magnitude of hundreds of volts), when devices made in this technology are used in switching applications. Basically, these voltage swings can cause the device island to deplete from the backside. Increasing the doping at the bottom of the device island helps to terminate any depletion field coming from the handle wafer on the backside of the device island. This allows for the device island to then deplete the drain extensions fully.
A p-type layer may be formed in the bottom of a lightly-doped p-type device island by doping the bottom of the device wafer before it is bonded to the handle wafer. See FIGS. 2a-2d. A disadvantage of this process is that the bottom p-type layer 12 will up-diffuse into the lightly doped p-type device wafer 10 during the growth of the bottom isolation (bond) oxide 14, and during the bonding process where the device and handle wafer are joined. These processes may have a large Dt (Diffusivity-time product) resulting in a thickening of the bottom p-type layer when boron is used as the p-type dopant 12.
Generally, in order to make high-voltage devices, junction depths must be scaled (made deeper) than for an equivalent device in a low-voltage process. Increasing junction depth, entails increasing Dt used in fabricating the devices. This also causes up-diffusion of a bottom p-type layer into the bulk of the lightly-doped p-type device island. The HVS process originally used a p-type (50 to 150 Ωcm) device island of about 35 to 40 μm thickness. Into this a p-type layer was implanted/diffused into the backside of the device wafer before the bond oxide is grown, after which the device wafer is bonded to the handle wafer.
In HVS, the backside p-type layer is put in before the wafer sees any of the Dt of the process. The first HVS full-process material was found (by SRP) to have the backside p-type layer that was not confined to within a few microns (μm) of the bottom of the device island (adjacent to the bond oxide), but that had up-diffused to nearly the surface of the lightly-doped p-type device island. This reduces the effectiveness of the backside p-type layer in enhancing the breakdown of the high-voltage devices.
The device island doping at the bottom needs to be restricted as closely as possible to the bottom of the device island (the device-Si/bond-oxide interface), so that high fields near breakdown are integrated over the greatest possible distance, and thus allow the maximum possible breakdown voltage. This leads to a penalty incurred for any thermal treatment (Dt) done after the backside p-type layer has been introduced. This is analogus to the unwanted up-diffusion of a buried layer. However, it should also be noted that the method and structure of this disclosure may be applied to current-carrying buried layers as well. The nature of bonded-wafer processing entails significant thermal treatment: device oxidation on the island bottom, bond oxidation during mating of the device/handle wafers, and trench sidewall oxidation to provide lateral device isolation. The thermal processing required for the front-side diffused layers further compounds the problem.
There are some obvious ways of mitigating the loss of breakdown due to up-diffusion of the backside p-type layer into the lightly-doped p-type device island Si. One is to lower the dose of the backside p-type (boron) implant. This does not correct the problem with up-diffusion, it just limits the concentration of dopant that is available for up-diffusion. Another way of keeping the backside p-type layer towards the bottom of the device island, is to increase the thickness of the device island. This is problematic for a couple of reasons. The trench etch must go through the entire thickness of the device island SL to provide lateral isolation for devices. Etching the isolation trench through a thicker device island, will result in more chance of small dimension device island geometries being undercut and delaminating from the handle wafer during subsequent processing. This results in an increase in the minimum device island size, and trench-to-trench minimum space, both of which result in a die area increase. The increase in trench depth also results in an decrease in equipment throughout at the trench etch operation.